1/4 rev. c structure product model functions semiconductor integrated circuit dsc/dvc system power lsi bd9639mwv (1) 6ch dc/dc converter ? ch1 boost fet embedded start-up ch,motor ? ch2 buck fet embedded core ? ch3 buck-boost fet embedded cmos ? ch4 buck-boost fet embedded digital ? ch5 buck fet embedded cmos, memory ? ch6 boost fet embedded led (2) low voltage operation 2.5[v] (3) ch1 supply voltage output for internal circuit (4) ch1 pwm/pfm selectable (5) ch3,ch4 boost-buck auto switching (6) ch6 integrated boost output shutdown (ch6 load switch embedded) (7) soft-start correspondence to each channel (8) ground short protection ch2 ch6 (9) error amp phase compensation(ch1 ch6) (10) operating frequency 1.5[mhz] (ch1 ch6) (11) package of mounting on high heat radiation side uqfn056v7070 absolute maximum ratings ta=25[ ] item symbol rating unit supply voltage vbat vbat2 ? 3 ? 4? 5 ? 6 -0.3 7 v sw6 permissible voltage sw6 24.0 v vout1 permissible current output i vout1 1.0 a sw1 permissible current output i sw 1.0 a sw2 permissible current output i sw2 2.0 a vout3 permissible current output i vout3 1.0 a dsw3 permissible current output i dsw3 1.0 a usw3 permissible current output i usw3 1.0 a vout4 permissible current output i vout4 1.0 a dsw4 permissible current output i dsw 1.0 a usw4 permissible current output i usw 1.0 a sw5 permissible current output i sw5 1.0 a sw6 permissible current output i sw6 0.2 a power dissipation pd 4.83 (*1) w operating temperature range topt -20 +85 storage temperature range tstg -55 +150 junction temperature tjmax +150 (*1) implemented on glass epoxy board rohm standard board 74.274.21.6[mm 3 ] 4 layers power dissipation depends on the mounted wiring pattern. operating supply voltage item symbol limit unit min typ max vbat supply voltage vbat 2.5 3.7 5.5 v vbat2 2.5 3.7 5.5 v vbat3 2.5 3.7 5.5 v vbat4 2.5 3.7 5.5 v vbat5 2.5 3.7 5.5 v vbat6 2.5 3.7 5.5 v no radiation-proof design
2/4 rev. c electrical characteristics unless otherwise specified vbat=vbat2,3,4,5,6=3.7[v] vcc=3.7[v] ta=25[ ] item symbol limit unit note min typ max current consumption (pfm) icc1 - 72 150 a ? xshdn1=h, xshdn24=l ? fb1=0.5[v] ? sum of vbat terminal, and vout1 terminal current consumption (pwm) icc2 1.57 2.35 3.53 ma ? xshdn1=h, xshdn24=h, test1=h ? fb1=0.5[v] ? sum of vbat terminal, and vout1 terminal shut current consumption icc3 - 0 10 a ? all setting terminal=l ? sum of vbat terminal, and vout1 terminal h input voltage 1 vih1 vbat -0.3 - - v xshdn1 l input voltage 1 vil1 - - gnd +0.3 v h input voltage 2 vih3 2.5 - - v xshdn24,xshdn3,xshdn5,xshdn6 l input voltage 2 vil3 - - gnd +0.3 v h input current 1 iih1 4.63 9.25 18.5 a power supply 3.7[v] xshdn24,xshdn3,xshdn5,xshdn6 oscillating frequency 1 fosc1 1.2 1.5 1.8 mhz rt=10[k ? ] reduced-voltage detection voltage vu vlo1 1.75 1.95 2.15 v reduced-voltage return voltage vuvlo2 1.95 2.15 2.35 v ch1 start-up time 85 tss1 310 620 930 s start-up period 100 730[us](typ) xshdn24=l error amp reference voltage eref1 0.388 0.400 0.412 v xshdn24=h pmos on resistance ronp1 - 0.24 0.38 ? power supply 3.7[v] nmos on resistance ronn1 - 0.14 0.23 ? power supply 3.7[v] maximum duty dmax 1 76.5 85.0 93.5 xshdn24=h ch2 error amp reference voltage eref2 0.390 0.400 0.410 v soft-start period 85 tss2 0.43 0.85 1.27 ms start-up period 100 1.0[ms] typ pmos on resistance ronp2 - 0.13 0.21 ? power supply 3.7[v] nmos on resistance ronn2 - 0.08 0.14 ? power supply 3.7[v] ch3 error amp reference voltage eref3 0.390 0.400 0.410 v soft-start period 85 tss3 0.85 1.70 2.55 ms start-up period 100 2.0[ms] typ pmos on resistance down side ronpd3 - 0.24 0.39 ? power supply 3.7[v] nmos on resistance down side ronnd3 - 0.25 0.40 ? power supply 3.7[v] pmos on resistance up side ronpu3 - 0.26 0.42 ? power supply 3.7[v] nmos on resistance up side ronnu3 - 0.16 0.27 ? power supply 3.7[v] maximum duty dmax3 65 80 95 ch4 error amp reference voltage eref4 0.390 0.400 0.410 v soft-start period 85 tss4 1.28 2.55 3.83 ms start-up period 100 3.0[ms] typ pmos on resistance down side ronpd4 - 0.16 0.26 ? power supply 3.7[v] nmos on resistance down side ronnd4 - 0.21 0.33 ? power supply 3.7[v] pmos on resistance up side ronpu4 - 0.24 0.38 ? power supply 3.7[v] nmos on resistance up side ronnu4 - 0.16 0.26 ? power supply 3.7[v] maximum duty dmax4 65 80 95 ch5 error amp reference voltage eref5 0.390 0.400 0.410 v soft-start period 85 tss5 0.85 1.70 2.55 ms start-up period 100 2.0[ms] typ pmos on resistance ronp5 - 0.26 0.42 ? power supply 3.7[v] nmos on resistance ronn5 - 0.17 0.28 ? power supply 3.7[v] ch6 error amp reference voltage 1 eref6 0.380 0. 400 0.420 v constant voltage control side error amp reference voltage 2 eref6.1 0.380 0.400 0.420 v constant current control side soft-start period 85 tss6 2.55 5.10 7.65 ms start-up period 100 6.0[ms]( typ) load switch on resistance ronp6 - 0.23 0.37 ? power supply 3.7[v] nmos on resistance ronn6 - 0.47 0.73 ? power supply 3.7[v] maximum duty dmax6 83 90 97
3/4 rev. c block diagram package outline terminal no./terminal name terminal description terminal no. name equivalent circuit terminal no name equivalent circuit 1 sw1 ch1 switching terminal o 29 fb6 ch6 feed buck terminal constant current side g 2 sw1 ch1 switching terminal o 30 pgnd6 ch6 driver gnd terminal g 3 pgnd1 ch1 driver gnd terminal g 31 sw6 ch6 switching terminal o 4 pgnd1 ch1 driver gnd terminal g 32 lso6 ch6 load switch output terminal o 5 test1 test terminal o ? g 33 vbat6 ch6 load switch input terminal v 6 vbat battery input terminal v 34 xshdn6 ch6 shutdown terminal o ? g 7 xshdn1 ch1 shutdown terminal g 35 rt triangle wave setting resistor terminal (*1) 8 agnd1 analog gnd terminal g 36 agnd2 analog gnd terminal g 9 xshdn24 ch2 ? 4 shutdown terminal o? g 37 vcc analog power supply terminal v 10 fb5 ch5 feed buck terminal g 38 pgnd2 ch2 driver gnd terminal g 11 pgnd5 ch5 driver gnd terminal g 39 pgnd2 ch2 driver gnd terminal g 12 sw5 ch5 switching terminal o 40 sw2 ch2 switching terminal o 13 vbat5 ch5 driver power supply terminal v 41 sw2 ch2 switching terminal o 14 xshdn5 ch5 shutdown terminal o ? g 42 vbat2 ch2 driver power supply terminal v 15 fb4 ch4 feed buck terminal g 43 vbat2 ch2 driver power supply terminal v 16 vout4 ch4 output terminal o 44 fb2 ch2 feed buck terminal g 17 vout4 ch4 output terminal o 45 test2 test terminal o ? g 18 usw4 ch4 boost side switching terminal o 46 xshdn3 ch3 shutdown terminal o ? g 19 usw4 ch4 boost side switching terminal o 47 vbat3 ch3 driver power supply terminal v 20 pgnd4 ch4 driver gnd terminal g 48 dsw3 ch3 buck side switching terminal o 21 pgnd4 ch4 driver gnd terminal g 49 dpg3 ch3 gate connecting terminal o 22 dsw4 ch4 buck side switching terminal o 50 pgnd3 ch3 driver gnd terminal g 23 dsw4 ch4 buck side switching terminal o 51 usw3 ch3 boost side switching terminal o 24 vbat4 ch4 driver power supply terminal v 52 vout3 ch3 output terminal o 25 vbat4 ch4 driver power supply terminal v 53 fb3 ch3 feed buck terminal g 26 dpg4 ch4 gate connecting terminal o 54 fb1 ch1 feed buck terminal g 27 reserve reserve terminal o ? g 55 vout1 ch1 output terminal o 28 fb61 ch6 feed buck terminal constant current side g 56 vout1 ch1 output terminal o the alphabet on a right edge of the above-mentioned te rminal explanation is processing of unused. o ???open g ??? gnd o? g ??? open or gnd v ??? power supply (vbat) (*1) ??? 10[k
]pull-down 9639 ?
4/4 rev. c instruction for use 1 board patterning ? vbat,vbat2,vbat3,vbat4,vbat5,vba t6 are must be connected to power supply on the board. ? vcc must be connected to vout1 output on the board. ? all pgnd and agnd must be connected to gnd on the board. ? all power supply line and gnd terminals must be wired with wide/ short pattern in order to achi eve substantially low impedance. 2. peripheral circuitry ? use low esr ceramic capacitor fo r bypass condenser between power supply and gnd te rminal and place capacitor right next to the ic pins. ? place external components such as l and c by ic with wide/short pattern. ? draw output voltage from each end of capacitor. ? causing short circuit at ch1 output will overload the external diode and may breakdown the component. prepare physical countermeasures by adding poli-switches and fuses to avoid excess current flow. 3 start-up ? keep light load condition by starting up the device. ? make it to pwm mode (xshdn24=l h) after ch1 is started up in pfm mode (xshdn1=l h), and the vout1 output voltage stands up. moreover, start it about the start of ch3 ? ch5 ? ch6 since the pwm mode (contain it simultaneously). 4 absolute maximum ratings ? the quality control of the product has exercised adequate care, however operating above the absolute maximum ratings of supply voltage and/or operational temperature range may cause decay and destroy the ic. if specific mode such that exceeding the absolute maximum rat ings is expected, please have physical countermeasure such as adding fuses and poli-switches etc. 5 thermal design ? take consideration of power dissipation at actual device usage to ensure the satisfactory thermal design margin. (refer page 6) 6 terminal to terminal short / mis-mounting ? while mounting ic on the board, check direction and shift of t he ic. if inadequately mounted, ic might be breakdown. additional ly short circuit from unwanted contamination at power supply and gnd and/or between any terminals also may cause the defect. 7 operating in strong electromagnetic field ? please pay attention using device in the strong el ectromagnetic field. device may cause malfunction. 8 thermal shut down.(tsd) ? main purpose of tsd is to shutting ic down from runaway effect. it is not to compensate or to protect ic itself . therefore, pl ease do not continuously operate the ic after tsd circuit is activated and/or premis e operations such that tsd ci rcuit function to be used. 9 inspection with set board ? while connecting capacitor to low impedance pins, please discharge ca pacitor by one process by another to prevent stressing the ic. while mounting and removing the ic to/from the board in the inspection process, be sure to turn off the power supply by each action. moreover equip ground e arth in assembling process for esd protection and handle with care during the test and/or transportation. 10 input terminals ? this ic is a monolithic ic, and has p + isolation and p substrate for the element separation. therefore, a parasitic pn junction is firmed in this p-layer and n-layer of each element. for example shown in below picture, the resistor or the transistor is connected to the terminal. w hen the gnd voltage potential is greater than the voltage potential at terminals a or b, the pn junction operates as a parasitic diode. in addition , the parasitic npn transistor is formed in said parasitic diode and the n layer of surroundi ng elements close to said parasitic diode. these parasitic elemen ts are formed in the ic because of the voltage relation. the parasitic element operatin g causes the wrong operation and destruction. therefore, please be careful so as not to operate the parasitic elements by applying lower voltage than gnd (p substrate) to input terminals. moreover, please apply each input terminal with lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage bei ng applied 11 usage of this product ? this ic is designed to be used in dsc/dvd application. ? upon using our product to equipments or devic es other than above mentioned application, pl ease be sure to consult with our sale s representative in advance. terminal a stray component gnd p + p p substrat e terminal a stray component terminal b stray component gnd p p substrat e cb gnd e terminal b e c b stray component gnd neighborhood component resistor transistor (npn) p + p + p + nnn n n n n implified ic structure
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